EDA / ASIC

ASIC Services

Spec. Development, Algorithm and IP Development, System Partitioning, Design Implementation – RTL Coding, Core Integration, Logic Synthesis, Power and Area Optimization, Layout, Backend Verification and Signoff, Test Program Development

EDA Services

Architecture and Functional Modeling, FPGA/PLD development, HDL ( Verilog, VHDL, MHDL), Software Code development, DFT (JTAG, MBIST, Scan Insertion), Schematic Capture, Synthesis Optimization, Placement Routing, RTL Simulation, Circuit Simulation, Mixed-signal Simulation, Delay Calculation, Static Timing Analysis, Gate-level Simulation, Power estimation, Verification of Specification

Sample Projects:

· Prototype testing of communication ASICs

· Unit level interface definition, circuit and PWB design, analysis and engineering model checkout for payload control processor unit.

· Embedded software/firmware programming including resource conflicts, concurrency, multi-tasking, and memory management.

· Improving Video Capture Timing by 4 times on Karaoke 40Mhz Board for image capture.

· ASIC verification of Decision Feedback Adaptive Equalizer for QPSK/QAM Modulation and CDMA Rake Receiver, path searcher.

· IC block architecture and transistor-level analog IC design verification Including circuit simulation, layout supervision and IC debug of bandgaps, delay and phased locked loops.